Re: VerilogAMS LRM2.3 Committee call agenda

Hi Sri,

Just a small issue, but the date in the call details is still at the 15'th
of November. I assume that should actually be the 29th of November, a.k.a.
today, as suggested by the start of your email?

Regards,
Marq

<>
<> Marq Kole Competence Leader Analog
Simulation
<> Philips ED&T/AS Consultant Circuit Optimization
<> Building WAY 3.069 phone: +31 40 27 44875
<> Professor Holstlaan 4 fax: +31 40 27 44700
<> 5656 AA Eindhoven e-mail: marq.kole@philips.com
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<>

Chandrasekaran Srikanth-A12788 <Srikanth.Chandrasekaran@freescale.com>
Sent by:
owner-verilog-ams@eda.org
29-11-2004 09:34
 
        To: Verilog-AMS LRM Committee <verilog-ams@eda.org>
        cc: (bcc: Marq Kole/EHV/RESEARCH/PHILIPS)
        Subject: VerilogAMS LRM2.3 Committee call agenda
        Classification:

Hi all,

Since I didn't receive any objection to the change in time (possibly
because most of the US was on holiday), I am tentatively scheduling
tomorrow's call at 1:30pm Pacific time. If this is inconvinient/short
notice, I can move the call for next week. If there is no response, I am
assuming everybody is okay with the call time.

Agenda:

* Merge with IEEE 2001 standard - discuss on the specific dates, sections
impacted and amount of resources
* Resolve the keyword conflict in discipline logic with SV - Expecting
proposal from Martin
* Updates to $table_model proposal.
* Extend mixed signal analysis scheduling semantics and algorithm for non
transient analysis (DCSweep, AC, Noise etc)

Call Details:
Date: 15 Nov 2004
Time: 1:30pm Pacific Time
Dialin Number & Passcode:
----------------------------------------
USA Toll Free Number: 877-346-8823
USA Toll Number: +1-203-320-0407 (for international call-in) PARTICIPANT
PASSCODE: 602538

Cheers,
Sri

--
Srikanth Chandrasekaran
Freescale Semiconductors, Australia
Ph: +61-8-8168 3592 Fax: 3501