RE: VerilogAMS LRM Committee Agenda - 17 Jan 2005 (1:30pm Pacific Time)

Hi Michael,

I discussed IBIS presentation in the VerilogAMS committee call this morning. Given your unavailability on Jan 31st, we will have the IBIS presentation on Feb 14th - given that the committee meets every two weeks. Hope this date is fine with you. It will be the regular time of 1:30pm pacific time.

Regards,
Sri

-----Original Message-----
From: Mirmak, Michael [mailto:michael.mirmak@intel.com]
Sent: Tuesday, 18 January 2005 3:09 AM
To: Chandrasekaran Srikanth-A12788
Subject: RE: VerilogAMS LRM Committee Agenda - 17 Jan 2005 (1:30pm Pacific Time)

Sri,

Just a quick item: the regular IBIS summit at DesignCon in Santa Clara, CA will be taking place on Monday, January 31. Needless to say, that day would not be available for an IBIS presentation to the Verilog-AMS team. :)

- MM

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of Chandrasekaran Srikanth-A12788
Sent: Sunday, January 16, 2005 11:03 PM
To: Verilog-AMS LRM Committee
Subject: VerilogAMS LRM Committee Agenda - 17 Jan 2005 (1:30pm Pacific
Time)

Hi all,

This is a reminder for tomorrow's VerilogAMS committee conference call.

Agenda:
* Discussions on updated $table_model
* Identifying timelines for IEEE 2001 syntax merger - updated BNF syntax (with compact model extensions to the original work is being sent by Graham).
* Fix date for IBIS presentation for interfacing with VerilogAMS

Date: 17 Jan 2005
Time: 1:30pm Pacific Time

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Cheers,
sri

--
Srikanth Chandrasekaran
Freescale Semiconductors, Australia
Ph: +61-8-8168 3592 Fax: 3501