Helwig Graham-A11558 wrote:
>
> The Verilog-2001 syntax avoids the use of italicization in it
> syntax description. I have made changes to the AMS syntax to
> avoid the use of italicization in order to be consistent with
> Verilog-2001. Regarding the real_identifier syntax item is
> defined in section A.9.3, there is not need to make the "real"
> part italic.
Ah, I see this now. Looking through A.9.3, it looks like a lot
of wasted space to define all the ???_identifier as just identifier,
but then I see that there are a few places where you can't use an
escaped identifier.
> From a syntax point of view, the LHS is just another
> parameter_identifier like the RHS. However readability is reduced.
> So I have made the following changes:
>
> alias_param_assignment ::= aliased_parameter_identifier = parameter_identifier
> aliased_parameter_identifier ::= parameter_identifier
Thank you. Not only readability, but the intent: it needs to
be clear which is the alias and which the true parameter, since
the module must use the true parameter in expressions.
> Can ddx() be used within indirect contribution statements?
Yes, I don't believe that should cause any problems for the
simulator -- though it seems odd that a user would do it,
asking the simulator to take the derivative rather than
doing it him/herself.
V(out) : ddx(expr, V(in)) == 0;
One could manually take the derivative of "expr" with respect
to V(in) and use that in an indirect contribution, so allowing
ddx in this way does not add any complications for the simulator.
-Geoffrey
-- Geoffrey J. Coram, Ph.D. Senior CAD Engineer Analog Devices, Inc. Geoffrey.Coram@analog.com 804 Woburn St., MS-422, Tel (781) 937-1924 Wilmington, MA 01887 Fax (781) 937-1014Received on Tue Jan 18 07:29:28 2005
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