Updated Syntax with Device Model updates (on behalf of Graham)

The PDF attachment from Graham's e-mail was too long for the
reflector, so I have placed it on the eda.org web site:

http://www.eda.org/verilog-ams/htmlpages/public-docs/syntax_2.3_draft.pdf

Graham's e-mail is below:

>From Graham Helwig:
>
> Hello Sri and others,
>
> The merged Verilog-AMS/Verilog-2001 syntax has been updated to include the compact modeling syntax introduced into LRM version 2.2. See attached PDF.
>
> Below are solme additional notes about the changes that were made:
> - String parameters have been inserted as another type of normal and local parameter declaration.
> - Alias parameter declarations now support multiple assignments in order to be consistent with other declarations.
> - Alias parameter declarations are not supported in the module_parameter_port_list syntax item.
> - Paramset declarations:
> - Does not support array parameter assignments.
> - change module_parameter_identifier to be parameter_identifier to be consist with rest of syntax.
> - String parameter declarations use string syntax item for the default expression (not string_constant_expression).
> - System parameter identifiers use the same naming convention as system function/task identifiers
> - Simplified the ddx() operator's optional 2nd argument syntax, use semantic check to restrict it further if required.
>
> Regards
> Graham
Received on Mon Jan 17 07:48:21 2005