RE: When does w change?

To continue on the last answer, and get back to the issue at hand, the
spec..
"continuous" doesn't mean what the Verilog-A guys would think it does.
And the paragraph should be expanded to clarify that the expression in
the assign statement can ONLY consist of variables/registers in the
Discrete aka Logic or Event domain.
I wouldn't expect transition sensitivity to be supported on an analog
value or expression.

Jonathan David Mixed-Signal IC
jbdavid@cadence.com Ph (408)894-2646

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of Bakalar, Kenneth
Sent: Friday, February 11, 2005 3:00 PM
To: verilog-ams@eda.org
Subject: When does w change?

All,

Here is a puzzle. At what series of simulation times is the process
associated with the "assign" executed?

module x;
  real e;
  wire w;
  analog e = sin($abstime);
  assign w = (e > 0.0);
endmodule

"6.1.2 The continuous assignment statement [Verilog 2001]

...Assignments on nets shall be continuous and automatic. This means
that whenever an operand in the righthand side expression changes value,
the whole right-hand side shall be evaluated and if the new value is
different from the previous value, then the new value shall be assigned
to the left-hand side..."

Regards,
Ken
Received on Fri Feb 11 16:25:45 2005