When does w change?

All,

Here is a puzzle. At what series of simulation times is the process
associated with the "assign" executed?

module x;
  real e;
  wire w;
  analog e = sin($abstime);
  assign w = (e > 0.0);
endmodule

"6.1.2 The continuous assignment statement [Verilog 2001]

...Assignments on nets shall be continuous and automatic. This means
that whenever an operand in the righthand side expression changes value,
the whole right-hand side shall be evaluated and if the new value is
different from the previous value, then the new value shall be assigned
to the left-hand side..."

Regards,
Ken
Received on Fri Feb 11 15:00:09 2005