Re: When does w change?

Ken,

Digging way back into discussions when Antrim was still a company (~1999)
and we were attempting to complete LRM 2.0 we found this to be bad form but
allowable. Users should "guard" this access to gain better control but
I've seen unguarded access work for certain situations.

Anyway at time zero "e" would be evaluated by the analog engine and trigger
an initial event that would set "w". Then since digital has no events
schedule the only time "w" would change would be a function of the analog
time step. At each analog time step "e" would be re-evaluated (and based
on the expression) and change value thus triggering an analog sensitivity
"event" in the digital world.

The problem is that each simulator has its own time step algorithm so
results would be a function of accuracy settings including the simulators
time step algorithm, not wrong just a function of. This can also be very
slow as the solvers end up working in lock step.

Note: section 6.1.2 is repeated in the AMS LRM in section
9.4.3.1 and this concurrency behavior is discussed in section 8.3, 9.3, and
9.4 although maybe more clarity is needed?

Jon

At 03:00 PM 2/11/2005, Bakalar, Kenneth wrote:
>All,
>
>Here is a puzzle. At what series of simulation times is the process
>associated with the "assign" executed?
>
>module x;
> real e;
> wire w;
> analog e = sin($abstime);
> assign w = (e > 0.0);
>endmodule
>
>
>"6.1.2 The continuous assignment statement [Verilog 2001]
>
>...Assignments on nets shall be continuous and automatic. This means
>that whenever an operand in the righthand side expression changes value,
>the whole right-hand side shall be evaluated and if the new value is
>different from the previous value, then the new value shall be assigned
>to the left-hand side..."
>
>
>Regards,
>Ken

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Jonathan L. Sanders
Product Engineering Director
Custom IC Solutions
Cadence Design Systems, Inc.
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  INTERNET:jons@cadence.com Tel: (408) 428-5654 Fax : (408) 944-7027
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Received on Sat Feb 12 10:01:51 2005