Summary of IEEE1364-2001 and 2005 syntax differences

From: Helwig Graham-A11558 <Graham.Helwig@freescale.com>
Date: Mon Feb 14 2005 - 15:26:27 PST

Hello,

Below is a summary of the changes between the syntax of IEEE1364 2001 and 2005 that impacts the AMS language. The biggest change that will need to be addressed is the reworking of the generate construct and resulting changes to the declaration and use of genvars.

Regards
Graham

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ANALOG AND DIGITAL SYSTEM TASK CALLS
------------------------------------

In section A.6.9, changes to arguments of a system_task_enable makes analog_system_task_enable syntax item inconsistent. Should they be aligned?

MODULE DECLARATION PORT LIST
----------------------------

In section A.1.3, the port list is now mandatory. Therefore the following example module declaration is not allowed. This results in backward compatibility issues for both existing digital, analog and mixed module declarations.

        module example1;
                ...
        endmodule
 
CHANGES TO GENERATE CONSTRUCT
-----------------------------

In section A.1.5, the generate constructs have been contained with generate regions and no genvar variable declarations are allowed within the module scope (only within the generate region). The AMS generate mechanism is dependent of the declaration of module scope genvars. Changes will need to be made to AMS language to align with the 2005 standard. Below are two possible modifications to AMS:

OPTION 1) Allow multiple analog blocks within a module declaration. Analog blocks can be used within generate regions so that the genvar variables can be accessed. As a result genvar variables can be used in either digital, analog or mixed contexts. After unrolling generate behavior during elaboration, the multiple analog blocks are concatenated into a single analog block in order of appearance within the module declaration. For example:

        module example2();
          generate
            genvar var;
          analog begin
            ...
            end
            initial begin
               ...
            end
          endgenerate
          analog begin
             ...
          end
        endmodule

OPTION 2) Continue to only allow one analog block within a module declaration. Allow procedural (no module instantiations are allowed) analog generate region(s) to be defined within a module's analog block to contain the analog generate/genvar behavior. Analog specific genvar declarations are used within analog generate region(s). A module's genvar variables can only ever be used in either digital or analog, never mixed contexts. Analog genvar for and conditional statements can only be used within analog generate regions within an analog block. For example:

        module example3();
          generate
            genvar var1;
            initial begin
               ...
          end
          endgenerate
          analog begin
              generate
             genvar var2;
             ...
            endgenerate
             ...
          end
        endmodule

Conditional instantiation of analog and mixed-signal modules in both of the above options is allowed within the module scope generate regions. For option 2, the analog block generate region allows only procedural analog statements only.

Neither option proposed here is backward compatible with version 2.3 of AMS. A backward compatible option has not been found yet.

ANALOG EVENTS IN GENERATE REGIONS
---------------------------------

Will analog events be allowed to be used within generate regions? If so, will the declared genvars within the generate be allowed to be used within these analog event sub-expressions? For example:

        module example4();
          parameter integer param = 6;
          generate
          genvar i;
             for (i=0; i<param; i=i+1) begin
                always @(timer(i)) begin
                 ...
               end
            end
          end
          ...
        endmodule

MINTYPMAX PARAMETERS
--------------------

The 2005 standard allows the declaration, overriding and use of mintypmax parameters. Is this type of parameter allowed within the analog block?

----------------------------------
Graham Helwig
Freescale Semiconductor
Phone: +61 8 81683532
Fax: +61 8 81683501
Eamil: graham.helwig@freescale.com
----------------------------------
Received on Mon Feb 14 15:27:05 2005

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