Re: analog vs digital domains of variables

My view is that "real x" is just a variable - the idea that it is (or
needs to be) analog or digital is an artifact of bad simulator design.
If it was a signal then its drivers and receivers would be analog or
digital.

A general principal in the design of Verilog-AMS is that any process
should be swappable with its analog (or digital) equivalent and that
doing so will not disrupt overall behavior and will require a minimum of
rewriting. A particular case in point is that it should be possible to
write testbenches which use cross-module references to probe (and set)
values in a design and the design can be implemented using either analog
or digital processes.

The LRM just needs to be clear about when assignments occur and which
value a process being evaluated will read from the assigned variable.

Kev.

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of Geoffrey.Coram
Sent: Thursday, February 17, 2005 8:10 AM
To: Chandrasekaran Srikanth-A12788; VerilogAMS Reflector
Subject: analog vs digital domains of variables

Hi, Sri -
A certain commercial simulator started complaining about
variables in my Verilog-A module that were declared but
not assigned a value.  The simulator took the view that
if the variable is not assigned a value in the analog
block (the analog context), then it is a digital variable.

However, in this case, the variable was *declared* in
a named block in the analog block.  Is it not clear in
this case that the variable belongs in the analog domain?
Is it legal to declare a variable in the analog block
and then assign a value to it in a digital context?
If not, then should section 8.2.2 explictly say the
domain is determined by where the variable is declared,
or if declared at module scope, by where it is assigned.

module am_i_legal(a);
  inout a;
  electrical a;
  analog begin : the_analog_block
    real x;
    V(a) <+ x;
  end

  initial begin
    the_analog_block.x=1;
  end
endmodule


-Geoffrey