RE: absdelay and changing td

From: Jonathan David <jbdavid_at_.....>
Date: Thu Mar 03 2005 - 07:23:07 PST
The last sentence is just wrong. The feature is not intended to be shape
preserving in the case where you have a variable delay. maybe this is
why I haven't ever used it, but I've had no real need to yet, a constant
delay has fit well every time I have used it so far.
 

Jonathan David   Mixed-Signal IC
jbdavid@cadence.com Ph (408)894-2646


 


________________________________

	From: owner-verilog-ams@eda.org
[mailto:owner-verilog-ams@eda.org] On Behalf Of marq.kole@Philips.com
	Sent: Thursday, March 03, 2005 7:02 AM
	To: VerilogAMS Reflector
	Subject: Re: absdelay and changing td
	
	

	Geoffrey, 
	
	I would definitely agree that the wording in the last two
sentences states that td is always ignored. 
	
	With respect to the intent, I can only guess, but I could
imagine that the delay would be mapped on precalculated timepoints and
that the maxdelay is used to get an optimal (shape-preserving) mapping
on current time-points? 
	
	Maybe it's a kind of an analogy to auto time series in a
transient simulation. For instance, the Newton iteration for a new time
point could create a solution at a delay time that that is not exactly
td, but will not be more than maxdelay. 
	
	The actual reason for using such a thing escapes me, though. 
	
	Regards, 
	Marq 
	
Received on Thu Mar 3 07:23:38 2005

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