RE: $finish and @(final_step())

For a $finish on the digital side, the analog simulation should just be
allowed to "free-run" until its stop time.

For a $finish in analog, Marq has summed it up pretty well.

 -- Scott


+++-----Original Message-----
+++From: owner-verilog-ams@eda.org 
+++[mailto:owner-verilog-ams@eda.org] On Behalf Of Tamhankar 
+++Prasanna-A14507
+++Sent: Thursday, April 21, 2005 3:57 AM
+++To: verilog-ams@eda.org
+++Subject: $finish and @(final_step())
+++
+++Hi all,
+++
+++LRM says "final_step generates global events only on the 
+++last point in an analysis" (section 6.7.4), however, should 
+++final_step  event trigger if a $finish is encountered ? 
+++Consider a case where say some files were opened (in 
+++initial_step) and are to be closed in final_step. If a 
+++$finish event happens before the simulator reaches the 
+++simulation end time, it will be nice to trigger the 
+++final_step so as to close all the files. 
+++
+++I have included two example modules below, the first one is 
+++purely analog, second one is mixed signal.
+++
+++module analogFinish;
+++
+++  analog begin
+++
+++    @(initial_step("static")) begin
+++       // some file opens
+++    end
+++    if ($abstime > 0.7) begin
+++      $strobe("%m About to call analog finish"); 
+++      $finish(0);
+++    end
+++
+++    @(final_step("tran")) begin
+++      $strobe("%m >> Time %g: '@(final_step('tran'))' event 
+++has fired.", $abstime);
+++      // some file closes
+++    end
+++  end
+++endmodule
+++
+++`timescale 1ms / 1ms
+++module digitalFinish;
+++  initial begin
+++     #700;
+++     $display("Time %g: Digital $finish(0) is about to 
+++occur.", $realtime);
+++     $finish(0);
+++  end
+++  analog begin
+++    @(initial_step("static")) begin
+++     // some file open
+++    end
+++    
+++    @(final_step("tran")) begin
+++      $strobe("%m >> Time %g: '@(final_step('tran'))' event 
+++has fired.", $abstime);
+++      // some file close
+++    end
+++  end
+++endmodule
+++
+++Also, in this module digitalFinish, assume that the analog 
+++and the digital engines synchronized at 0.6 seconds. Analog 
+++takes a step to say 0.74 seconds and then the digital tries 
+++to catch up, but at 0.7 (#700) encounters a $finish. Should 
+++the analog  engine then synchronize with digital by 
+++backing-up from 0.74 to 0.7 and then end the simulation ?
+++
+++Best regards,
+++Prasanna
+++
+++