Hi all, Agenda: - Mixed signal IC and non-transient analyses proposal discussion (http://www.eda.org/verilog-ams/htmlpages/public-docs/sched_2.1.pdf) - Table_model discussions (updated proposal hasn't yet been sent out) - Annex G, Open items in reflector, Inboxes and moving to the system used in SV (Regards to point #3 I am not sure whether its been set up for VerilogAMS - Also I havent had much time to look at the various different lists and collate them, but still we can quickly browse through the Annex G open issues list). Call Details: Date: 24 May 2005 (Tuesday), 3:00pm US Pacific Time Dialin Number & Passcode: ---------------------------------------- USA Toll Free Number: 877-346-8823 USA Toll Number: +1-203-320-0407 (for international call-in) PARTICIPANT PASSCODE: 602538 Regards. -- Srikanth Chandrasekaran Freescale Semiconductors, Australia Ph: +61-8-8168 3592 Fax: 3501Received on Tue May 24 01:58:14 2005
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