Re: Draft proposal for (1) Mixed-signal IC analysis (2) Mixed-si gnal non-transient analyses

Hello all,

Can you send me any feedback on the draft proposal please ?  Thanks for all the discussion we had during the last call. 

Cheers,
Prasanna 
------------------------------------------------------
Prasanna Tamhankar
Freescale Semiconductors, Adelaide
+61 8 81683585
------------------------------------------------------ 

> -----Original Message-----
> From: owner-verilog-ams@eda.org 
> [mailto:owner-verilog-ams@eda.org] On Behalf Of Tamhankar 
> Prasanna-A14507
> Sent: Tuesday, 24 May 2005 11:41 AM
> To: verilog-ams@eda.org
> Subject: Draft proposal for (1) Mixed-signal IC analysis (2) 
> Mixed-signal non-transient analyses
> 
> 
> Hi All,
> 
> Please click on the link below for the draft proposal for 
> 
> 	(1) Mixed-signal IC analysis 
> 	(2) Mixed-signal non-transient analyses
> 
> http://www.eda.org/verilog-ams/htmlpages/public-docs/sched_2.1.pdf
> 
> Please note that I have based this draft on section 9 of LRM 
> 2.1 (instead of section 9 of LRM 2.2) because I didn't have 
> the frame version of LRM 2.2 when I was writing the proposal. 
> I don't think anything has changed in Section 9 between 2.1 
> and 2.2. I have the latest 2.2 frame version now for section 
> 9, I will re-send this proposal basing it on 2.2 along with 
> any feedback people have later. 
> 
> Also, I have the text "<TBD cross ref>" in a few places, 
> please ignore this, this is only for myself so that I 
> actually make these Frame cross references in the final version.
> 
> We can discuss this proposal during our next call, 
> Best regards,
> Prasanna
> ------------------------------------------------------
> Prasanna Tamhankar
> Freescale Semiconductors, Adelaide
> +61 8 81683585
> ------------------------------------------------------ 
>