Hi all, I plan to postpone the meeting scheduled for 7th June and have the next one on the 21st of June. The status of the following items are as follows: 1. AC, DCSweep MS proposal - Martin's feedback was received just now. I don't think there is sufficient time for australia to analyse this before discussion tomorrow morning (australian time). No further feedback on this. 2. Table_model proposal: No update on this. Current Status: Requirements have been clarified (& frozen), waiting for the updated proposal. 3. Migrating open issues to SV-AMS system: No update on this, as far as I know, this hasn't yet been setup for Verilog-AMS. I am thinking I will go ahead and just for the time being send out the spreadsheet format again which can be discussed in the next call 4. Cadence SV-AMS Strawman proposal: No updates on this yet. Regards, Sri -- Srikanth Chandrasekaran Freescale Semiconductor, Inc., Australia Ph: +61-8-8168 3592 Fax: 3501Received on Tue Jun 7 00:57:39 2005
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