RE: Draft proposal for (1) Mixed-signal IC analysis (2) Mixed-signal non-transient analyses

Prasanna,

Here is my feedback.

Thanks,
--Martin

First of all thanks for writing this - think it is good that the mixed
signal initialization process is clearer in the LRM.

9.2.2
Think it would be better to use another name other than initial
condition analysis because what you describe seems more to be an
operation point calculation/analysis or mixed signal initialization.

9.3.1.1

The method describe seems similar to that of Verimix which seeks to
co-simulate blocks describe in languages that are not naturally
mixed-signal. Verilog-AMS, however, is a mixed-signal language so
something cleaner is possible.

The LRM already describes later in section 9.3 how analog and digital
naturally synchronize based on d2a and a2d events.

The same approach can be applied quite naturally to mixed-signal
initialization as follows;

1: Set initial conditions for analog nodes
2: Run digital kernel until all events at t=0 are
exhausted
3: Do a DC solution in analog kernel
4: If there no zero-delay A2D events goto 7:
5: Run digital kernel until all events at t=0 are
exhausted
6: If there are zero-delay D2A events goto 3:
7: end of mixed-signal initialization

Note that digital is left run first so that the t=0 assignments can be
done to eliminate many of the 'x's.

In terms of continuing simulation until no x's are left - this is not
necessary and might also not be what the users want.

Note that Verilog-AMS CMs can be written to naturally handle 'x's.

9.5.1.1
As stated about 9.3.1.1, I think the proposal for getting mixed signal
initialization should be changed - this would also apply to getting the
operating point.

9.5.1.2 Point 1;
I see the changes mentioned above about how to do mixed signal
initialization also applying here.

9.5.1.2 Point 2;
Re-evaluating initial blocks in digital seems wrong and dangerous to me.
In Verilog initial blocks are only intended to be run once - they can
also contain delayed assignments which could cause chaos if scheduled
more that once by running an initial block multiple times.

9.5.1.2 Point 3;
My take is that it is an open question whether users would like the a2d
events processed by digital and d2a events potentially passed back. I
can see reasons for going both ways so maybe it should be an option the
user has.

9.5.1.3
I see the changes mentioned above about how to do mixed signal
initialization also applying here to get an operating point.

Re-evaluating initial blocks in digital seems wrong and dangerous to me.
In Verilog they are only intended to be run once.

During a small signal analysis, it should be stated that digital
maintains it state, doesn't advance time and that no A2Ds or D2As are
generated.

9.5.1.4
This seems like a reasonable approach to me. However it seems like a
good idea to state that the digital engine and state are fixed/frozen
when a small signal analysis is done after a transient analysis and that
no A2Ds or D2As are generated.

Thanks,
--Martin

>-----Original Message-----
>From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
>Behalf Of Tamhankar Prasanna-A14507
>Sent: Monday, May 23, 2005 7:11 PM
>To: verilog-ams@eda.org
>Subject: Draft proposal for (1) Mixed-signal IC analysis (2)
Mixed-signal
>non-transient analyses
>
>Hi All,
>
>Please click on the link below for the draft proposal for
>
>	(1) Mixed-signal IC analysis
>	(2) Mixed-signal non-transient analyses
>
>http://www.eda.org/verilog-ams/htmlpages/public-docs/sched_2.1.pdf
>
>Please note that I have based this draft on section 9 of LRM 2.1
(instead
>of section 9 of LRM 2.2) because I didn't have the frame version of LRM
2.2
>when I was writing the proposal. I don't think anything has changed in
>Section 9 between 2.1 and 2.2. I have the latest 2.2 frame version now
for
>section 9, I will re-send this proposal basing it on 2.2 along with any
>feedback people have later.
>
>Also, I have the text "<TBD cross ref>" in a few places, please ignore
this,
>this is only for myself so that I actually make these Frame cross
>references in the final version.
>
>We can discuss this proposal during our next call,
>Best regards,
>Prasanna
>------------------------------------------------------
>Prasanna Tamhankar
>Freescale Semiconductors, Adelaide
>+61 8 81683585
>------------------------------------------------------