Hi all, After a break of AMS committee meetings, probably its time to re-start discussions on moving forward with the AMS standards. Also there have been lot of emails on new topics, work, donations and probably good time to start the committee meetings. I have also collated a list of open issues - based on the items that were sent to me and through the reflector. Hopefully I have covered most of the issues including the recent issues being discussed - verilog-ams testsuite, spice compatibility etc. I have not put it in the system that they use for SV that David Smith suggested (mantis database), since I havent chased it up with David to get it setup. Hence went back to the true and trusted excel spreadsheet format. Agenda: * How do we move forward - release of AMS versions with minor enhancements, SV integration, 1364 integration? * Mixed Signal IC analysis - there has been feedback from Martin on this * $table_model enhancements - no further updates * Verilog-AMS validation suite * Donation of VerilogA versions of spice primivites specified in Table E.1 from Marq. * If there is time we can go through the list of open issues - probably this will be taken up in the next meeting. With regards to open issues, there are some very simple items that can be fixed. So we can try to prioritize and see whether there are anybody who are interested in working on proposals for certain items listed in the spreadsheet. Call-In Details: Time & Date: 26th July, 3pm Pacific Time Dialin Number & Passcode: USA Toll Free Number: 877-346-8823 USA Toll Number: +1-203-320-0407 (for international call-in) PARTICIPANT PASSCODE: 602538 Regards, Sri -- Srikanth Chandrasekaran Freescale Semiconductor, Inc., Australia Ph: +61-8-8168 3592 Fax: 3501
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