Proposal to resolve SV and Verilog-AMS conflicts in array literal definitions

Here is a proposal to resolve another SV/Verilog conflict, that for
array literals.
I am cc'ing one of the Cadence SV reps as he is familar with this issue.
 
Thanks,
--Martin
 
Issue:
====
SV and Verilog-AMS both define array literals in a different manner.
They are used by AMS in as default values for parameter arrays, for
passing values to parameter arrays and as array arguments to system
tasks such as $zi_*, $laplace*.
 
As SV and Verilog-AMS are targetting to join together in the future, it
is best for all concerned to address this discrepency in the next
revision of the LRM so as to minimize the amount of potential migration
work that users will have to do.
 
Description:
========
In SV a ' is required before the opening curly brace whereas in AMS it
is not - the ' was needed in SV to avoid a parser ambiguity between
array literals and concatenations. The SV committee want to use the AMS
approach but the parser ambiguity precluded this.

Example;
 
AMS:
parameter real poles[0:3] = { 1.0, 3.198, 4.554, 2.00 };

SV:
parameter real poles[0:3] = '{ 1.0, 3.198, 4.554, 2.00 };
                            ^ notice the tick!!               
Proposal:
=======
It is proposed that Verilog-AMS LRM changes the existing Verilog-AMS
array parameter syntax so that a ' is required in order to be consistent
with SV.
 
Not requiring the ' should be noted in the deprecated syntax section of
the Verilog-AMS LRM.
 
The deprecated syntax section should also state that simulators which
support deprecated features must issue an "archaic syntax warning" when
such features are used. This is needed in order to promote better
standardization.