proposal to resolve AMS - SystemVerilog logic conflict

 
Here is my proposal to resolve AMS - SystemVerilog contradictory uses of
logic declarations
Thanks,
--Martin


Problem: 
AMS and SystemVerilog both use 'logic' in a contradictory way.

This prevents people for mixed AMS and SystemVerilog in the same parse
stream.

It also is going be a serious roadblock for creating SystemVerilog-AMS.

In AMS, logic is discipline defined in the standard discipline header
file; disciplines.vams;

	discipline logic
	domain discrete;
	enddiscipline

To make declare a net called n as having logic discipline in AMS one
does;

	logic n;

SystemVerilog adds another 4-value data type, called logic (see Sections
3.3.2 and 5.6 of the SystemVerilog 3.1a LRM).

To create a logic variable called n, one does;

	logic n;

Note logic is almost exactly identical to 'reg' except logic can be
declared inside other things (like a struct).


Solution:

We need to deprecate logic as a identified defined in disciplines.vams;

In AMS, the definition of logic as a discrete discipline in
disciplines.vams should be removed.

Also the following should be added the disciplines.vams to promote a new
standard discrete discipline called d_logic (short for discipline logic)
but allow users to switch back to using logic by putting "'define
VAMS_DISCRETE_DIS logic" before the include to disciplines.vams in their
sourcefiles.

`ifdef VAMS_DISCRETE_DIS
`else
`define VAMS_DISCRETE_DIS d_logic
`endif

discipline `VAMS_DEFAULT_DISCRETE_DIS
     domain discrete;
enddiscipline

All examples/text in the LRM that use logic should be changed to
d_logic.