RE: parameter definition in user-defined function

Prasanna,

You're right, of course: k++ is C, Verilog-A does not even know about the 
k+=1 operation so needs the full k=k+1.

However, my point is that Verilog-AMS does not need to be updated with 
respect to array arguments in analog functions: the BNF shown in section 
4.6 and Annex A fully supports the use of array arguments, it is just that 
the LRM section 4.6 never mentions even the possibility, and I presume it 
has therefore escaped most implementers - my question was to verify this 
assumption.

Now LRM 2.2 allows output arguments, there is even no need for an array 
return type in the function. An open issue, however, is how to create 
parametrized array length for analog functions.

Anyway, I'll add something abotu this to the Mantis database as soon as I 
have access.

Regards,
Marq


Marq Kole
Competence Leader Analog Simulation, Philips ED&T









Tamhankar Prasanna-A14507 
17-08-2005 09:39

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Marq Kole/EHV/RESEARCH/PHILIPS@PHILIPS
verilog-ams@eda.org
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Subject
RE: parameter definition in user-defined function
Classification







Hi Marq,

          analog begin 
            for (k = 0; k <= 3; k++) begin 
 <snip>
Is there - by the way - any simulator currently around that can correctly 
handle the above (legal!) Verilog-A code? 
 
No sir, not legal with k++ in there ;-) (should be k=k+1). 
 
Coming to the question of being able to pass in arrays into analog 
functions, I think this should be supported in Verilog-AMS. Please go 
ahead and add this to the mantis database ( http://www.eda.org/mantis/ )
 
Best regards,
Prasanna