Typo in section 7.14 SystemVerilog 3.1a ?

Hi,

Don't know how to report typos in SystemVerilog LRM, so I am copying Steven Sharp too.

On SV LRM section 7.14, in the example,

module mod1;
  typedef struct {
    int x;
    int y;
  } st;


  st s1;
  int k = 1;


  initial begin

    #1 s1 = {1, 2+k}; // by position
    #1 $display( s1.x, s1.y);
    #1 s1 = {x:2, y:3+k); // by name
    #1 $display( s1);
    #1 $finish;
  end
endmodule

Shouldn't the highlighted line be

    #1 s1 = {x:2, y:3+k}; // by name
Regards,

Prasanna
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Prasanna Tamhankar
Freescale Semiconductors, Adelaide
+61 8 81683585
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