hierarchical parameter passing in DC sweep

All,

Currently, I have the following piece of Verilog-A code, essentially a 
test bench for the resistor primitive written in Verilog-A in such a way 
that the actual test environment is in Verilog-A, requiring only a minimal 
stub of simulator code itself.

`ifdef OUT_FILE
`else
`define OUT_FILE "test_out.txt"
`endif

module vdc1 (p, n);
inout p, n;
electrical p, n;
parameter dc = 0.0;

  analog
    V(p, n) <+ dc;

endmodule // vdc1

module resistor1 (p, n);
inout p, n;
electrical p, n;
parameter r = 1k;

  analog
    if (r != 0)
      I(p, n) <+ V(p, n) / r;
    else
      V(p, n) <+ 0;

endmodule // resistor1

module driver_dcsweep (a, b);
inout a, b;
electrical a, b;
parameter real param = 0.0;

  electrical p, n;

  vdc1 #(.dc(param * 1.0)) E1 (p, n);
  resistor1 #(.r(1k)) R2 (p, n);

  integer fn;

  analog begin

    // Open the file before starting the test.
    @(initial_step("dc")) begin
      if (!fn)
        fn = $fopen(`OUT_FILE);
      if (!fn) begin
        $strobe("ERROR: couldn't open file '%s', aborting.", `OUT_FILE);
        $finish;
      end
      $fstrobe(fn, "%s\t\t%s", "V", "param");
    end

    // Print out the voltage, current and calculated resistance.
    $fstrobe(fn, "%e\t%e", V(p, n), param);

    // Close the file before ending the test.
    @(final_step("dc")) begin
      $fclose(fn);
    end

  end // analog

endmodule // driver_dcsweep

Now instantiating the driver_dcsweep in a top-level netlist in the 
simulator and sweeping the parameter param of the driver_dcsweep instance 
from 1 to 5 with steps of 1, I expected the output file test_out.txt to 
contain a table of values for the voltage across the resistor and the 
value of param. However, it turned out that the value of param even though 
updated at the top-level is not passed on to the lower level, i.e. the 
instance of vdc shown here. I could not find any reference to this in the 
2.2 LRM, but this seems to me a perfectly reasonable use of a parameter 
sweep.

Before entering another issue in the Mantis database, I'd thought that I'd 
better collect some input from the list.

Also, it seems that the Verilog-A capable simulators I have at my disposal 
have very different opinions about handling the above code. The terminals 
a and b are dummy terminals, the actual circuit is a voltage source across 
a resistor between terminals p and n.

Regards,
Marq


Marq Kole
Competence Leader Analog Simulation, Philips ED&T