RE: Clarification question

Arpad, Sri,

I'm confused by you confusion :-)

In my opinion what is meant in 3.2.4 is that if you create a module that 
takes an array parameter, when you instantiate that module you and you 
want to provide a particular value for that array parameter, the array 
provided as input has to be of the same length as the one declared in the 
module heading.

Furthermore, the LRM allows parameter-sized arrays of ports and 
parameters, so you can control the length of an array parameter through an 
additional (integer) parameter:

module andn(a, b);
parameter integer n = 2 from [2:inf);
inout[0:n-1] a;
inout b;
electrical[0:n-1] a;
electrical b;
parameter real delaytime[0:n-1] = { 20n, 22n };

...

The above construct where the parameter n appears right after the module 
heading is allowed, and required in order to use parameter n in subsequent 
port and parameter declarations.

Above is a bit constructed example, where you define an AND gate with 
per-input delays. Now if you instantiate above AND module, you know 
already the size of the array of delays because in the same instance you 
have to provide the width of the array through the parameter n, so again 
paragraph 3.2.4. applies without any issue I can see.

I am not aware that a situation can exist where a reference to an array 
cannot know beforehand the size of the array it needs to address, but if 
such a situation can arise, then a system function to collect the length 
of an array would be required. One item where it appears, but that is not 
directly language related, is in the vpwl and ipwl sources mentioned in 
Annex E - however there is at the moment no requirement to be able to 
create Verilog-AMS modules for each of these primitives.

Now given that you already know about n, the issue of for-loops and array 
indexing is trivial.


Marq Kole
Competence Leader Analog Simulation, Philips ED&T










Chandrasekaran Srikanth-A12788 <Srikanth.Chandrasekaran@freescale.com> 
Sent by:
owner-verilog-ams@eda.org
09-09-2005 06:49

To
"'Muranyi, Arpad'" <arpad.muranyi@intel.com>
verilog-ams@eda.org
cc

Subject
RE: Clarification question
Classification








Hi Arpad,

1. Re: to different instances having different parameter sizes:

(In my opinion) parameters are instance specific post elaboration. Today, 
parameters belonging to different instances can have different values - 
overridden as part of instantiating the module. Going by the same 
argument, I would guess that the same parameter can have different sizes 
in different instances. So if the same module is instantiated multiple 
times each instance that owns the parameter will have different sizes. 

Couple of other issues on this:
  1a. Ofcourse, I would assume that the parameter was declared as a vector 
to being with? I am not sure whether this restriction should be there or 
not. One reason is, vector parameters need to have a type associated with 
it as part of the declaration, which is not required for scalars. Not sure 
whether that's the only constraint or not.

  1b. If the width is resized, lets say we have parameter real P[0:N] = 
...; where N is a parameter, and N is overridden as part of the hierarchy, 
I guess the user would be required to provide the new RHS expression for 
the parameter also for the new size.

  1c. What does digital do? I am not so sure about how digital handles all 
this.

Once again in my opinion (looks like I have lots of them today) this 
resizing the parameter array on an instance basis looks confusing and 
clumsy to begin with. But I guess we will keep the language 
spec/support/implementation consistent with what digital LRM says, so that 
we don't have to deviate.

2. Re: obtaining size of array

If you are looking for some kind of system function in the language, I 
don't think there exists any. Its an interesting question tho', if the 
designer wants to loop over all the elements of the vector parameter, they 
should already know the information on the size of the vector.

3. 1364-2001 features - fscanf, sscanf

These functions are not supported in analog as part of the LRM today. Part 
of the work we are doing with integrating the language with 1364-2005 is 
to get the languages (analog & digital) to be consistent. I agree we are 
bit behind on this in terms of AMS language development, but the plan is 
to migrate to the most recent digital standard so that the features are 
available in both analog and digital.

Regards,
Sri 



-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On 
Behalf Of Muranyi, Arpad
Sent: Friday, 9 September 2005 1:36 PM
To: verilog-ams@eda.org
Subject: RE: Clarification question


Sri,

Thanks for your attempt to answer my questions.

So if we assume that the LRM says what we read into it,
i.e. you can assign a different size of an array to the parameter, 
regardless of what the size in its declaration is and it should resize 
because of that, is it also possible to declare a parameter in the module 
to be a certain size and then at the time it is instantiated pass a 
different size of an array into the module?  If so, what happens if the 
module is instantiated multiple times and each time it is instantiated a 
different size of an array is passed into its parameter?

I would also like hear your (or anyone else's) opinion about
my questions on for loops and reading data tables in files
into arrays.  Can these be done?  I couldn't find a way to
do this so far... 

Thanks,

Arpad ==========================================================

-----Original Message-----
From: Chandrasekaran Srikanth-A12788 
[mailto:Srikanth.Chandrasekaran@freescale.com] 
Sent: Thursday, September 08, 2005 5:30 PM
To: Muranyi, Arpad; verilog-ams@eda.org
Subject: RE: Clarification question

Hi Arpad,

Okay - that sentence is extremely convoluted and I really don't understand 
what it exactly means. Infact I tried reading bullet point #2 in the same 
section "An array assigned to an instance of a module shall be of the 
exact size of the array bounds of that instance" in reference to parameter 
arrays. Not exactly clear what this means either.

I am giving a few examples which probably will invoke some discussion on 
how it should behave. The LRM is not very clear on the semantics of this - 
probably the above bullet points are the semantics which are difficult to 
understand :-),

  parameter integer P[0:2] = {0,1};
            (or)
  parameter integer P[N:1] = {1,2,3}; // where N is another parameter, 
lets say N resolves to 2

I would have expected that both of the above cases would be an error where 
the size of the expression on the right hand side is not the size defined 
as part of the range expression for the parameter. The LRM (I think) seems 
to suggest that the parameter array should be resized based on the 
parameter assignment expression on the RHS.

Its also possible that vector parameters can be overridden in the child 
instantiation line, for example:

  child #(.P(Q)) chld1(a,b); // where P & Q are vector parameters of 
different sizes. I would have thought this will also be an error.

Any other thoughts on what those bullets mean?

Any ideas as to how digital behaves in these cases?

Regards,
Sri



-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On 
Behalf Of Muranyi, Arpad
Sent: Friday, 9 September 2005 8:35 AM
To: verilog-ams@eda.org
Subject: Clarification question


Hello everyone,

Sorry for a few novice questions.

This sentence in the LRM got me.  Could someone please help
me to understand it (perhaps with some simple examples)?
This is in section 3.2.4:

"If the array size is changed via a parameter assignment, the parameter 
array shall be assigned an array of the new size from the same module as 
the parameter assignment that changed the parameter array size."

First, I would like to understand how the size of an array can be changed. 
 Second, I would like to understand the second half of the sentence that 
deals with the assignment, and module.

Also, is there a way to obtain the size of an array, for example for the 
purpose of running a for loop as many times as the number of elements in 
the array?

Seemingly unrelated, question:  Is there a way to read data tables from 
files into arrays, kind of like the $table_model function does it?  I have 
seen the $fscan, $sscan, etc... functions in the 1364-2001 manual, but are 
those officially available and supported by "Verilog-AMS" tools?


Thanks,

Arpad ==================================================================