RE: Clarification question

Mark,
 
Thanks for your explanation.  I can't speak for Sri, but my
confusion stems from the first part of the sentence in the
LRM:  "If the array size is changed via a parameter assignment, ..."

To me (and probably many others who are just starting to learn
the language) this translates into something like this:
parameter real myarrayparam[0:1] = {1.0, 2.0, 3.0, 4.0, 5.0};

After all, I am doing a parameter assignment in the above line,
right?  And since the size of the array being assigned is
different from the original size of the parameter it should
resize, right?  I knew it right away that this doesn't look
right, yet I was completely lost because there is no example
in the LRM to show how that sentence can be coded.  This is
why I posted my question.  Take this as a request to add an
example or a better description to the LRM.  Your example
would be very appropriate and needed in this section.

The second part of that sentence just adds to the confusion.
It should really be a separate sentence, or even paragraph.
Looking at your example, it is starting to make sense now, but
without understanding the first step, it is completely nonsense.

Regarding the array size question, there are numerous situations
when the array size is not known beforehand.  That's why most
modern programming languages have functions to get the size of
the array, and have even resizable arrays.  If this was never
needed, no programming language would have features like that.

Take, for example, a file read operation.  I want to read a
data table from a file, similar to how $table_model does it,
except I want it to read the data into array(s) so I can further
process it.  The length of the table in the file is not known
beforehand.  How would you do this (provided that file parsing
functions are available, which I am just finding out that they
are not)?

Sincerely,

Arpad
================================================================


________________________________

From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of Marq Kole
Sent: Friday, September 09, 2005 12:15 AM
To: verilog-ams@eda.org
Subject: RE: Clarification question



Arpad, Sri, 

I'm confused by you confusion :-) 

In my opinion what is meant in 3.2.4 is that if you create a module that
takes an array parameter, when you instantiate that module you and you
want to provide a particular value for that array parameter, the array
provided as input has to be of the same length as the one declared in
the module heading. 

Furthermore, the LRM allows parameter-sized arrays of ports and
parameters, so you can control the length of an array parameter through
an additional (integer) parameter: 

module andn(a, b); 
parameter integer n = 2 from [2:inf); 
inout[0:n-1] a; 
inout b; 
electrical[0:n-1] a; 
electrical b; 
parameter real delaytime[0:n-1] = { 20n, 22n }; 

... 

The above construct where the parameter n appears right after the module
heading is allowed, and required in order to use parameter n in
subsequent port and parameter declarations. 

Above is a bit constructed example, where you define an AND gate with
per-input delays. Now if you instantiate above AND module, you know
already the size of the array of delays because in the same instance you
have to provide the width of the array through the parameter n, so again
paragraph 3.2.4. applies without any issue I can see. 

I am not aware that a situation can exist where a reference to an array
cannot know beforehand the size of the array it needs to address, but if
such a situation can arise, then a system function to collect the length
of an array would be required. One item where it appears, but that is
not directly language related, is in the vpwl and ipwl sources mentioned
in Annex E - however there is at the moment no requirement to be able to
create Verilog-AMS modules for each of these primitives. 

Now given that you already know about n, the issue of for-loops and
array indexing is trivial. 


Marq Kole
Competence Leader Analog Simulation, Philips ED&T