RE: Clarification question

Arpad

> Thanks for your explanation.  I can't speak for Sri, but my
> confusion stems from the first part of the sentence in the
> LRM:  "If the array size is changed via a parameter assignment, ..."
> 
> To me (and probably many others who are just starting to learn
> the language) this translates into something like this:
> parameter real myarrayparam[0:1] = {1.0, 2.0, 3.0, 4.0, 5.0};
> 
> After all, I am doing a parameter assignment in the above line,
> right?

No, this is a parameter (array) initialization, it looks the same, but 
behaves differently. Verilog-AMS requires that all parameters are given 
initial values. The only way to change the values in the above example is 
by instantiating the module that contains the above parameter declaration 
and instantiation.

In C++ there is an analogous situation: if you state:

  const istream istr = std::stdin;

you do not actually call the assignment operator, but rather the copy 
constructor. Essentially, while it looks like you are allowed to "assign" 
to a constant value, it is just providing the constant value of this 
particular const variable.

If a module writer would create a statement:

  parameter real myarrayparam[0:1] = {1.0, 2.0, 3.0, 4.0, 5.0};

it would obviously be a wrong initialization of the two values in 
myarrayparam.

Inside the module body, you cannot do an assignment to this array 
parameter anymore, nor of any other parameter. Parameters are constant 
after being initialized. Instantiating a module that takes an array 
parameter only means that you provide a different initializer for that 
array parameter, which takes priority over the default initializer.

>  And since the size of the array being assigned is
> different from the original size of the parameter it should
> resize, right?  I knew it right away that this doesn't look
> right, yet I was completely lost because there is no example
> in the LRM to show how that sentence can be coded.  This is
> why I posted my question.  Take this as a request to add an
> example or a better description to the LRM.  Your example
> would be very appropriate and needed in this section.
> 
> The second part of that sentence just adds to the confusion.
> It should really be a separate sentence, or even paragraph.
> Looking at your example, it is starting to make sense now, but
> without understanding the first step, it is completely nonsense.
> 
> Regarding the array size question, there are numerous situations
> when the array size is not known beforehand.  That's why most
> modern programming languages have functions to get the size of
> the array, and have even resizable arrays.  If this was never
> needed, no programming language would have features like that.
> 
> Take, for example, a file read operation.  I want to read a
> data table from a file, similar to how $table_model does it,
> except I want it to read the data into array(s) so I can further
> process it.  The length of the table in the file is not known
> beforehand.  How would you do this (provided that file parsing
> functions are available, which I am just finding out that they
> are not)?

Reading from a file (except for the table-model) is not supported in LRM 
2.2 and earlier. I would rather say that there are actually very few - if 
any - occasions where an array size cannot be known beforehand. The one 
you stated is not really LRM 2.2 as it depends on 1364-200x functionality, 
instead of the 1364-1995 used as a basis in the 2.x releases of 
Verilog-AMS.

As it is, I cannot think up any example in pure Verilog-AMS that requires 
knowledge of the size of the array and no ability to determine it other 
than from the array itself. Would be interested to hear anyone else that 
has such an example.

> 
> Sincerely,
> 
> Arpad

Regards,
 
Marq Kole
Competence Leader Analog Simulation, Philips ED&T