Re: Multi-dimensional arrays?

From: Sri Chandra <srikanth.chandrasekaran_at_.....>
Date: Tue Sep 13 2005 - 05:32:29 PDT

Hi,

Just deviating a little bit from the topic of multi-dimensional parameter array - since shalom made a reference to net arrays - With regards to net declarations, AMS also supports multi-dimensional nets - however this is semantically restricted in the analog context...This is mainly supported in AMS to mainly allow the declaration of memories (if somebody is wondering). Syntactically one could do electical [0:3] analogNetA [0:7] - however this is semantically restricted. This syntax is more used in 2-D memory register in the digital context.

regards,
Sri

Bresticker, Shalom wrote:

Again, in 1364-200x, variable and net arrays are defined, but not
parameter arrays.

Shalom


  

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
    

Behalf Of Geoffrey.Coram
  

Sent: Tuesday, September 13, 2005 2:21 PM
To: Muranyi, Arpad; VerilogAMS Reflector
Subject: Re: Multi-dimensional arrays?

Arpad -
Perhaps no one on this list has tried/wanted multi-dim arrays.

If it's supported in 1364-200x, then again, I would expect
that some vendors of AMS simulators would have upgraded
the AMS side to go along with the digital standard, and
it would work.

I'm fairly sure the LRM doesn't include the syntax, but
you can read as well as the rest of us.

-Geoffrey


"Muranyi, Arpad" wrote:
    

Since I posted this question I found some information
on multi dimensional arrays, and it seems that the
declaration would go something like this:

     real myMultiDimArray[1:3][1:2];

However, I still wonder whether this is available for
parameters in Verilog-AMS, and if so, what the syntax
is to initialize the elements?  Could someone please
answer the question?

     parameter real myMultiDimArray[1:3][1:2] = ???;

Thanks,

Arpad
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Received on Tue Sep 13 05:33:14 2005