Re: Minutes of LRM Committee Meeting - Sept 13/14th 2005

Since we were discussing mixing discipline assignments with in/out etc. 
on arrays I thought I'd suggest how to assign different disciplines to 
different slices of an array (should anyone want to do it).

In SystemVerilog there is an alias statement, in theory you could do 
something like:

       ....
       wire [5:0]foo;
       alias foo[5:3] = f1[2:0];
       alias foo[2:0] = f2[2:0];
       disc_a f1[2:0];      // attribute discipline disc_a to top wires
       disc_b f2[2:0];      // attribute discipline disc_b to bottom wires

Trying to do something like V(foo[i]) where V is an access function 
would probably be illegal (since you would maybe have to pick the 
implementation of V dynamically), but V(f1[i]) or V(f2[i]) are OK.

Kev.