RE: Verilog-AMS/2005 syntax and keywords

"Bresticker, Shalom" <shalom.bresticker@intel.com> wrote on 30-09-2005 
15:37:53:

<SNIP> 

> >>3) '\n' has been added to end of the syntax for each
> >directive.
> [Shalom: ] This assumes that each directive may not be followed by
> additional text on the same line. While it is true for `define and a
> couple of others, I am not sure it is true for all. We did discuss this
> in 1364. I think we did not want to require this in order not to make
> illegal existing legacy code.

Most Verilog-A simulators allow following an `endif directive with a 
comment (useful for nested structures or very large pieces of text between 
the `ifdef and the `endif). Having the '\n' to end the syntax would break 
this.

On the other hand, this is the only deviation I know of that works and is 
used often...

Marq