RE: Verilog-AMS question regarding $table_model

Hi Muranyi,

$table_model() does a multidimensional interpolation on a dataset argument
using the present values of its lookup arguments and so I would agree with
you, it does not need to follow the restrictions of analog operators.

There may have been valid reasons to restrict it in 2.2, so perhaps someone
involved in the 2.2 definition may provide some background. Assuming there
are no reasons to restrict $table_model(), then in 2.3 we should remove the
last paragraph of 10.12. 

Regards,

Patrick

Patrick O'Halloran
Tiburon Design Automation
patrick@tiburon-da.com
707-694-2013 (cell)
707-541-7343 (office)

 

> -----Original Message-----
> From: owner-verilog-ams@eda.org 
> [mailto:owner-verilog-ams@eda.org] On Behalf Of Muranyi, Arpad
> Sent: Friday, October 07, 2005 12:12 PM
> To: verilog-ams
> Subject: Verilog-AMS question regarding $table_model
> 
> Hello again,
>  
> I would like to ask a question about the restrictions imposed 
> on the $table_model function.
>  
> The last paragraph of Section 10.12 of the LRM v2.2 says the
> following:
>  
> "The $table_model system function has the same restrictions 
> as analog operators in terms of where it may be used - i.e. 
> it shall not be used inside if, case or for statements unless 
> these statements are controlled by genvar-constant 
> expressions. See Section 4.4 for more details on the 
> restrictions on analog operators."
> 
> I simply do not understand the reason for needing this restriction.
> My understanding is that $table_model is a lookup function, 
> and it does not depend on any past values from previous 
> iterations, like ddt or idt do.  Is this restriction 
> justified?  I am leaning towards requesting the removal of 
> this restriction, but first I want to ask the question in 
> case I don't know about something that justifies this restriction.
> 
> Thanks,
> 
> Arpad
> ===================================================================
> 
>