Verilog-AMS question regarding $table_model

Hello again,
 
I would like to ask a question about the restrictions imposed
on the $table_model function.
 
The last paragraph of Section 10.12 of the LRM v2.2 says the
following:
 
"The $table_model system function has the same restrictions as analog
operators in terms
of where it may be used - i.e. it shall not be used inside if, case or
for statements unless
these statements are controlled by genvar-constant expressions. See
Section 4.4 for more
details on the restrictions on analog operators."

I simply do not understand the reason for needing this restriction.
My understanding is that $table_model is a lookup function, and it
does not depend on any past values from previous iterations, like
ddt or idt do.  Is this restriction justified?  I am leaning towards
requesting the removal of this restriction, but first I want to ask
the question in case I don't know about something that justifies this
restriction.

Thanks,

Arpad
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