Re: Using logic in power-up circuitry

I think you've run across an old problem that was never addressed 
properly. The fault is on the digital side since there is no way to 
indicate that a wire/signal is actually a power supply within the 
language, and that kind of thing is usually left to the backend tools. 
Basically Verilog pre-dates the kind of power control now present on ICs.

The search algorithm for an OOMR something like "power.vdd" will match 
the first module instance called "power"  in the hierarchy directly 
above the reference, i.e. you don't need the full hierarchal path if you 
place the power signals in a module which is instantiated in the 
hierarchy above the connect module rather than being directly in the 
hierarchy.

That's a bit awkward because you probably  don't want to have to add in  
extra power instances, so it would be nicer to have new OOMR syntax 
something like "^.<signal>" (^. being a single operator) which would 
just look for the first instance of the named signal in the hierachy 
above the current module. You also probably want to mark power signals 
as such so that the backend tools can use them correctly. Then you 
should be able to write code like:

    power wire vdd; // power is a keyword indicating the signal is the 
local vdd power

    wire power_on; // control

    vdd = power_on ? ^.vdd    // connect local power to parent power 
when needed
                                    : 1'bZ;

Kev.

Helwig Graham-A11558 wrote:

>Hello,
> 
>I have encountered a design where digital blocks are used as part of the power-up circuitry. When this design is  simulated with normal connectmodules erroneous behavior results because the connectmodules assumes static supply voltage but in reality the supply voltage is below the static voltage and it is dynamic. 
>
>In an attempt to avoid this erroneous simulation results, the net within the power-up digital block was changed to use the "logic_powerUp" discipline instead of "logic" discipline. Now a new set of connectmodules to interface "electrical" and "logic_powerUp" ports are required. The problem is how can these new connectmodules be made sensitive to the supply voltage?
>
>Using parameters are not suitable because the supply voltage is dynamic and parameters are static. There is no LRM mechanisms to define global nets and access them within the connectmodule. OOMRs can be used within a connectmodule, but this is very restrictive since the name of the supply net and design block in which it is located needs to be fixed. Connectmodules port list does not allow passing in an addition supply pin and the connectrules have no mechanism to determine which supply net is to be connected at the supply port at the time of connectmodule insertion.
>
>The only solution at the moment is to convert the digital block be fully analog at the cost of simulation performance. Is there a way continue using the digital block and make the inserted connectmodule instantiations supply sensitive?  If not, should the Verilog-AMS language be extended to provided this capability? 
>
>Regards
>Graham
>
>
>  
>