Using logic in power-up circuitry

Hello,
 
I have encountered a design where digital blocks are used as part of the power-up circuitry. When this design is  simulated with normal connectmodules erroneous behavior results because the connectmodules assumes static supply voltage but in reality the supply voltage is below the static voltage and it is dynamic. 

In an attempt to avoid this erroneous simulation results, the net within the power-up digital block was changed to use the "logic_powerUp" discipline instead of "logic" discipline. Now a new set of connectmodules to interface "electrical" and "logic_powerUp" ports are required. The problem is how can these new connectmodules be made sensitive to the supply voltage?

Using parameters are not suitable because the supply voltage is dynamic and parameters are static. There is no LRM mechanisms to define global nets and access them within the connectmodule. OOMRs can be used within a connectmodule, but this is very restrictive since the name of the supply net and design block in which it is located needs to be fixed. Connectmodules port list does not allow passing in an addition supply pin and the connectrules have no mechanism to determine which supply net is to be connected at the supply port at the time of connectmodule insertion.

The only solution at the moment is to convert the digital block be fully analog at the cost of simulation performance. Is there a way continue using the digital block and make the inserted connectmodule instantiations supply sensitive?  If not, should the Verilog-AMS language be extended to provided this capability? 

Regards
Graham