RE: Constant initialization question

If it helps any, Verilog-2001 did not allow built-in system functions in
constant expressions, but Verilog-2005 allows the built-in math
functions and the conversion functions to be used in constant
expressions.

Shalom


>-----Original Message-----
>From: owner-verilog-ams@eda.org [mailto:owner-verilog-
>ams@eda.org] On Behalf Of Muranyi, Arpad
>Sent: Monday, November 14, 2005 11:03 PM
>To: Verilog-AMS LRM Committee
>Subject: RE: Constant initialization question
>
>Thanks.  I found what I needed at the very
>beginning of chapter 4:
>
>"Some statement constructs require an expression to be a
>constant expression. The
>operands of a constant expression consists of constant numbers
>and parameter names,
>but they can use any of the operators defined in Table 4-1,
>Table 4-17, and Table 4-18."
>
>Arpad
>==========================================
>
>-----Original Message-----
>From: geoffrey.coram@analog.com
>[mailto:geoffrey.coram@analog.com]
>Sent: Monday, November 14, 2005 12:33 PM
>To: Muranyi, Arpad
>Cc: Verilog-AMS LRM Committee
>Subject: Re: Constant initialization question
>
>It is clear from the LRM, that is, it's explained in the
>formal syntax.  In a quick glance, I didn't see anything
>in section 4 about constant_expression versus expression,
>so I don't think that's the right place for it.
>
>-Geoffrey
>
>
>"Muranyi, Arpad" wrote:
>>
>> Well, I just got word from the compiler vendor that
>> they fixed the problem.
>>
>> However, I still wonder, is it clear from the LRM
>> that if all arguments to the math functions are
>> constants, the return value is also going to be a
>> constant?  Correct me if I am wrong, but I don't
>> recall any of this mentioned in the LRM (section 4.2).
>> There is a lot about integer/real, but I didn't
>> see anything on constant/variable.  Should
>> something like this be described in this area to
>> avoid any confusions?
>>
>> Thanks,
>>
>> Arpad