Static connections to input ports

Hello,

The Verilog language seems to allow the connection of a 4-state value to discrete input port within a module instantiation. See the first port connection in the example below. This type of port connection is very useful. The syntax of port connections in the IEEE-1364-2005 standard allows this type of port connection but there is little detail about it in body of the document.

Currently Verilog-AMS LRM v2.2 syntax does not allow this type of the port connection. The upcoming merger of the Verilog-AMS LRM 2.2 and 1364-2005 will correct this but it is unclear if equivalent types of port connections are allowed for wreal and continuous input ports. For example:
  
     module testbench();
          example i1(1'b1, 0.1, 3.1);
     endmodule
  
     module example(p1, p2, p3);
         input p1; logic p1; wire p1;
         input p2; logic p2; wreal p2;
         input p3; electrical p3;
     endmodule
  
NOTE: The static values in these wreal and continuous input port connections are handled in the same way as initialization values in explicit wreal and continuous net declarations.
  
Should the merged Verilog-AMS/2005 LRM support the static connections to all types of input ports?
  
Regards 
Graham Helwig
AMS Verification Engineer
Australia SoC Technology Centre
Freescale Semiconductor
 
Phone: +61-8-81683532
Fax: +61-8-81683201
Email: graham.helwig@freescale.com