RE: SV future

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Tue Nov 29 2005 - 23:57:57 PST
I don't know if Kevin was referring to these, but I think these may
answer your needs.

Regards,
Shalom
 

>-----Original Message-----
>From: owner-verilog-ams@eda.org [mailto:owner-verilog-
>ams@eda.org] On Behalf Of Muranyi, Arpad
>Sent: Wednesday, November 30, 2005 1:41 AM
>To: edaorg@v-ms.com; verilog-ams@eda.org
>Subject: RE: Static connections to input ports
>
>Kevin,
>
>Is this presentation available somewhere for
>viewing?
>
>Thanks,
>
>Arpad
>=============================================
>
>BTW, the last presentation I saw on the future of SV indicated
>that
>there might not be a single (System)Verilog LRM, but rather the
>SV and
>Verilog LRMs would continue as seperate entities, so targeting
>Verilog
>200X for AMS might be problematic if your goal  is actually
>merging with SV.
>
>Kev.

Received on Tue Nov 29 23:58:38 2005

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