Re: Definition of integer division

Jonathan David wrote:

>Kind of bothers me though.. 
>I can think of a circuit case for 1 combined with 0 = x 
>(two active outputs on the same wire) 
>but not for 1/0 = x.. 
>In the case of realhardware for which you might want
>the model to behave this way, I can fix it in the UDP
>- don't need the language defined this way.. 
>
The rationale is probably that n/0 is going to be invalid so you might 
as well make it x's and let it propagate.

>-- 
>seems to me what we REALLY want here is a way to flag
>an exception to the operation, and the provide for a
>way to handle it.. 
>for integer math, returning x is a kludge in this
>direction and might be good enough. 
>I agree in the analog domain its not much better than
>dieing with a div0 error.. 
>  
>
In regular Verilog nearly everything is 4-state so the x's should just 
propagate until they cause a noticeable failure in simulation or vanish 
(due to not being propagated farther), so there is no real reason to 
handle div0 errors specially - tools like Debussy would point you at the 
div0 error fairly quickly.

The addition of 2-state types is fairly recent, and the type conversion 
(4->2 state) was not thought through thoroughly. The solution (IMO) is 
to revamp the type system for SV/AMS so that all type conversions are 
user definable for user-defined types as well as predefined types i.e.: 
there should be no default conversion for 4->2 state, and users should 
be able to define it on a per-file/per-module basis. 

>---
>Isn't there a better way to handle operation
>exceptions like divide by zero?
>Just asking.. sorry!
>Jonathan.. 
>  
>
If SystemVerilog had continued on it's original track and incorporated 
C++ after C rather than branching off into Vera then you would have had 
the option of overloading '/' to do the div0 check and stop or throw an 
exception, you would also be able to overload '=' for 4 -> 2 state 
assignment.

Maybe you should be using SystemC-AMS :-)

Kev.