arithmetic surprise?

All,

I've found a piece of very simple looking Verilog-A code which 
nevertheless produces some very interesting results without giving a 
compilation error/warning or a run-time error/warning. Just try performing 
a DC simulation with the following model:

`include "constants.h"
`include "discipline.h"

module arith (a, b);
inout a, b;
electrical a, b;

integer ii;

analog begin

  @(initial_step) begin
    ii = 15;
    $display("ii = %d, (ii-16)/2*`M_PI = %g", ii, (ii-16)/2*`M_PI);
  end

end

endmodule // arith

I have found erroneous answers with at least two simulators: is this 
something that needs attention in the standard?

Regards,
Marq


Marq Kole
Competence Leader Analog Simulation, Philips ED&T