Re: arithmetic surprise?

From: Marq Kole <marq.kole_at_.....>
Date: Fri Jan 27 2006 - 06:16:02 PST
Geoffrey,

You're completely right. I even tested this in C and also C gives the 
answer 0 instead of `M_PI/2. The origin of this problem is probably that 
in our in house simulator all numbers are automatically interpreted as 
reals. As local warning I will probably suggest people add .0 to any 
integer that is going to be used in a real expression.

Sorry for bothering...

Regards,
Marq









"Geoffrey.Coram" <Geoffrey.Coram@analog.com> 
Sent by:
owner-verilog-ams@eda.org
26-01-2006 19:35

To
Marq Kole/EHV/RESEARCH/PHILIPS@PHILIPS
cc
verilog-ams <verilog-ams@eda.org>
Subject
Re: arithmetic surprise?
Classification







Marq -
My simulator gives the correct answer, which is zero.  If you are 
expecting
a non-zero answer, then you probably need to re-read the postings on
"integer division" started by Arpad a short while ago. :)

(ii-16) is an integer, 2 is an integer, so (ii-16)/2 is integer division
and yields 0.  Now, since `M_PI is a real, the 0 is coerced to a real
to perform the multiplication.

-Geoffrey


Marq Kole wrote:
> 
> All,
> 
> I've found a piece of very simple looking Verilog-A code which 
nevertheless produces some very interesting results without giving a 
compilation error/warning or a run-time error/warning. Just try performing 
a DC simulation with the following model:
> 
> `include "constants.h"
> `include "discipline.h"
> 
> module arith (a, b);
> inout a, b;
> electrical a, b;
> 
> integer ii;
> 
> analog begin
> 
>   @(initial_step) begin
>     ii = 15;
>     $display("ii = %d, (ii-16)/2*`M_PI = %g", ii, (ii-16)/2*`M_PI);
>   end
> 
> end
> 
> endmodule // arith
> 
> I have found erroneous answers with at least two simulators: is this 
something that needs attention in the standard?
> 
> Regards,
> Marq
Received on Fri Jan 27 06:17:45 2006

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