RE: discipline vs signal name conflicts

I think that one of the basic principles in Verilog/SystemVerilog is
that you cannot use the same identifier in the same scope for different
meanings, even if in principle you could distinguish between them by how
they are used.

Shalom


> -----Original Message-----
> From: owner-verilog-ams@eda.org [mailto:owner-verilog-
> ams@eda.org] On Behalf Of Geoffrey.Coram
> Sent: Monday, January 30, 2006 4:26 PM
> To: j.david@ieee.org
> Cc: verilog-ams
> Subject: Re: discipline vs signal name conflicts
> 
> Jonathan -
> 
> > in here the default access function for the "charge"
> > nature is defined to be "Q"..  which creates a problem
> 
> I've had a similar problem; in my case, the C code I was trying
> to
> convert to Verilog-A had a variable called "Acc" which is the
> access function for acceleration.
> 
> It seemed to me that the compiler should be able to distinguish
> between the two identifiers, since the access function always
> requires parentheses: Acc(porta,portb).  But I think SV has
> some new constructs, forget what they're called (methods?),
> where you can write Acc.function() to get some information
> about Acc, and one could imagine both parameters and access
> functions having such constructs.
> 
> 
> > IE my favorite simulator doesn't make it easy (not
> > impossible but not easy!!) to customize the default
> > displpines file so that this problem is eliminated..
> 
> Isn't it trivial to fix disciplines.h?  I mean, the first line
> of all my V-A files is `include "disciplines.h" and I could
> certainly replace that with `include "mydisciplines.h"
> 
> 
> -Geoffrey