Updated section 2 (Lexical conventions)

Hello,

The merged PDF for Section 2 (Lexical conventions) can be found at:

http://www.eda.org/verilog-ams/htmlpages/public-docs/merged_lex.pdf

Meaning behind of the various color coded text is:
- Black: Verilog-AMS LRM 2.2 text.
- Blue: added text either from 1364-2005 or other updates.
- Red strike through: Remove Verilog-AMS LRM 2.2 text.

Below is  the comments, issues and question as a result of the merger:
1) section 2.3: Removed comment syntax to be consistent with 1364-2005.
2) section 2.5: Updated the number syntax.
3) section 2.5: Will the full SI scaled factor notion be supported in 
Verilog-AMS?
4) section 2.5.1: Replace Verilog-AMS description with 1364-2005 
description since all types of integer numbers can be used in analog 
parameters, analog instances and analog blocks.
5) section 2.5.2: Extended description to include scale factor notation 
and table.
6) section 2.5.2: 1364-2005 description does not restrict the use of 
whitespace between the number and the scientific notation (e.g. 3.4 
e-9). To be consistent I have removed the equivalent whitespace 
restriction for scaled factor notation (e.g. 3.4 u). Should a 
restriction be added for both scenarios?
7) section 2.5.2: Verilog-AMS description has an additional underscore 
character restriction in real constants. 1364-2005 does not? Why is this 
restriction not in 1364-2005?
8) section 2.5.3: Added "conversion" section from 1364-2005.
9)  section 2.6: What is different between Verilog strings and strings 
in analog string parameters (last sentence in first paragraph)? Is the 
cross reference incorrect?
10) section 2.6.2: Updated last paragraph in the Verilog-AMS description 
with the 1364-2005 description.
11)  section 2.6.3: Added addition description for "\ddd" special 
character.
12) section 2.7: Added addition 1364-2005 description to end of paragraph.
13) section 2.7.3 and 2.7.4: Update syntax and description based on 
1364-2005.
14) section 2.7.3 and 2.7.4: Should 1364-2005 should be directly cross 
referenced in the Verilog-AMS LRM?
15) section 2.8:  Updated Verilog-AMS attribute description in line with 
1364-2005.
16)  section 2.8.1: Should the text be organized to more easily append 
newly identified standard Verilog-AMS attributes?
17) section 2.8.2 and 2.8.3: Added sections from 1364-2005 and updated 
the syntax.

Regards
Graham

-- 
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Graham Helwig
AMS Verification
Australian Semiconductor Technology Company (ASTC) Pty Ltd

Location: 76 Waymouth St, Adelaide, SA, 5000, Australia
Phone     +61-8-82312782
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Email:    graham.helwig@astc-design.com
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