Question about above() and cross()

At the risk of getting rotten eggs thrown at me, I would like
to raise a question about the above() and cross() functions.
This is in light of "compatibility" between the two AMS
languages, Verilog-AMS and VHDL-AMS.  Some of us have a need
to write the same model in both languages (or translate to one
from the other) and similarity between the two languages would
make our life a lot easier...

In VHDL-AMS there is a 'above attribute which returns a Boolean
signal true or false.  The return value will change depending on
the condition being true or false, regardless whether the change
is due to a rising or falling edge.  The returned signal being
a signal can be used in processes (event handlers) which are
triggered regardless of the direction of the change.

Contrast this with the Verilog-AMS above() function.  From 
Section 6.7.5.2 of the v2.2 LRM, the above() function
"... generates a monitored analog event to detect threshold
crossings in analog signals when the expression crosses
zero (0) from below."

Which means that it detects only rising edges, which is different
from the VHDL-AMS 'above.

I know there is a cross() function which can do both, but that
one has a limitation that it doesn't generate interrupts in DC
sweeps.  The 'above of VHDL-AMS does it regardless which analysis
it is used in.

I wonder whether we could address problems like this to be as
compatible between the two languages as possible to make the
model maker's (translator's) life easier?

Thanks,

Arpad
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