RE: Question about above() and cross()

Would it even work? abs(sig) will never cross 0 from
below, because its least value is 0.. 
you could do @(above(expression) or
above(-expression)) with the obvious drawback that
this will ALWAYS be true at DC.. 

Anyone for a Python inspired AMS-HDL ? 
(MyHDL already exists - so MyHDL-AMS?) 
maybe we could get away from all those "begin-end"
statements!

sorry to have missed the last couple of calls.
Jonathan

--- "Muranyi, Arpad" <arpad.muranyi@intel.com> wrote:

> Geoffrey,
> 
> Thanks for the trivial solution example.  I wonder
> though, how efficient it is?  It seems that the
> condition in the IF statement will need to be
> evaluated twice at EVERY analog iteration this
> way.  I could perhaps do @(above(abs(expr))) but
> this will also need an extra calculation for each
> iteration.  Not knowing too much about the internals
> of simulators I am curious how much this costs
> computationally?
> 
> Thanks,
> 
> Arpad
>
=====================================================
> 
> 
> -----Original Message-----
> From: geoffrey.coram@analog.com
> [mailto:geoffrey.coram@analog.com] 
> Sent: Wednesday, April 12, 2006 9:45 AM
> To: Muranyi, Arpad
> Cc: Verilog-AMS LRM Committee
> Subject: Re: Question about above() and cross()
> 
> Arpad -
> I didn't like above(); I had hoped to get cross()
> extended somehow
> to trigger in dc analysis, but there was a
> backwards-compatibility
> concern.
> 
> Of course, trivially,
>   @(above(expr) or above(-expr))
> will trigger for a crossing in either direction.
> 
> 
> -Geoffrey
> 
>