RE: Clarification question on port direction

Shalom,

Thanks for your reply.  No, I am not interested in Verilog-1995,
I am asking about the Verilog-AMS v2.2 LRM.  And no, I wasn't
asking about whether this can be done within the port definition
line of the module:

     module MyResistor (inout p, inout n);

because I know that this is not allowed in Verilog-AMS (unlike in
other languages).

What I wanted to know is whether it is required to add the input,
output, and/or inout declarations after the module definition:

    module MyResistor (p, n);
      electrical p, n;
      inout      p, n;

If so, I would also like to get some help in determining what
makes an analog port input or output.  For example, consider a
resistor module as shown in the example above.  Is the "p"
port supposed to be an input and the "n" port an output, considering
a positive current flow convention of p to n, or are they both
output, or inout?  I didn't see too much on this in the Verilog-AMS
v2.2 LRM.

Thanks,

Arpad
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-----Original Message-----
From: owner-verilog-ams@server.eda.org [mailto:owner-verilog-ams@server.eda.org] On Behalf Of Bresticker, Shalom
Sent: Thursday, May 04, 2006 2:45 AM
To: Muranyi, Arpad; VerilogAMS Reflector
Subject: RE: Clarification question on port direction

Arpad,

If I understand correctly, you are looking at a description of
Verilog-1995 syntax. In that case, port directions may not be described
in the module header. IF you have ports, then they must be described in
input, output, or inout declarations.

The case where you would not have them is if you write a module without
any ports. This is a common case. Top-level modules of testbenches, for
example.

Shalom