In Reality It should make little difference to the behavioral model. I would do ALL ports of device models as inout. Above that level, I do it mostly for convenience of the REST of the design database. I know many schematic capture tools have checks to make sure that no 2 outputs are shorted together, so if you have something like an open collector output, you make it an inout. Also a schematic will fail checks if you connect an input port to the output of a block inside, or if you have a bunch of input signals on blocks and the net connecting them is NOT connected to one block output or inout, or to an input port. inside an AND gate, I would make Ap, An, Bp, Bn all INPUT, as well as Vbias (or Ibias) .. Vdd, Vss would be inout, and Yp, Yn would be OUTPUT, unless I put the load resistors OUTSIDE the gate, then I would make them INOUT.. (This is of course a CML AND gate!) Now if I make (as I have in the past) a VAMS model of the block, Ap, An, are of (discrete) discipline cmlogic_a, Bp, Bn are cmlogic_b, and Yp, Yn are cmlogic_a - unless I build in the level shifter (with a level shift resistor in the output) then its cmlogic_b.. Ah, here is where I want the CROSS_SENSITIVITY type connect_module.. So the logic of Ap, An can be determined from the Supply, the ground and the other input.. Although for Cmos CML, one could model the input capacitance to simulator ground, rather than local ground! and use the ground sensitivity of each for the other? Doesn't work for Bipolar though. - base current would need to go to ground. Jonathan (Maybe I'll make this my BMAS paper this year?) --- "Muranyi, Arpad" <arpad.muranyi@intel.com> wrote: > Shalom, > > Thanks for your reply. No, I am not interested in > Verilog-1995, > I am asking about the Verilog-AMS v2.2 LRM. And no, > I wasn't > asking about whether this can be done within the > port definition > line of the module: > > module MyResistor (inout p, inout n); > > because I know that this is not allowed in > Verilog-AMS (unlike in > other languages). > > What I wanted to know is whether it is required to > add the input, > output, and/or inout declarations after the module > definition: > > module MyResistor (p, n); > electrical p, n; > inout p, n; > > If so, I would also like to get some help in > determining what > makes an analog port input or output. For example, > consider a > resistor module as shown in the example above. Is > the "p" > port supposed to be an input and the "n" port an > output, considering > a positive current flow convention of p to n, or are > they both > output, or inout? I didn't see too much on this in > the Verilog-AMS > v2.2 LRM. > > Thanks, > > Arpad > ====================================================================== > > > > -----Original Message----- > From: owner-verilog-ams@server.eda.org > [mailto:owner-verilog-ams@server.eda.org] On Behalf > Of Bresticker, Shalom > Sent: Thursday, May 04, 2006 2:45 AM > To: Muranyi, Arpad; VerilogAMS Reflector > Subject: RE: Clarification question on port > direction > > Arpad, > > If I understand correctly, you are looking at a > description of > Verilog-1995 syntax. In that case, port directions > may not be described > in the module header. IF you have ports, then they > must be described in > input, output, or inout declarations. > > The case where you would not have them is if you > write a module without > any ports. This is a common case. Top-level modules > of testbenches, for > example. > > Shalom > >Received on Thu May 4 12:52:20 2006
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