Hello Geoffrey, Apologies for not attending the last call. I have not had time yet to go into a detailed look of the changes, so the following notes should be followed up with some more later. Hopefully my feedback back below will be useful and its not doubling up on the discussions in the call. 1) One minor thing, I suggest changing the following syntax format to avoid any potential confusion. From: syntax_item ::= syntax_description (From Annex A.x.x) to: syntax_item ::= (From Annex A.x.x) syntax_description I don't think 1365-2005 puts the section reference after the one-liner syntax statement. 2) Regarding the structure of the chapter, I understand that disciplines and natures are closely tied with nets, but they are data types on there own right. So I suggest changing the structure to: 3 Data types 3.1 Integers and Reals 3.2 Parameters 3.3 Genvars 3.4 Natures 3.5 Disciplines 3.6 Nets 3.7 Branches 3.8 Namespace The "Nets" section describes the extension to the 1364-2005 net declarations. This section would include "default discipline", "discipline precedence", "real net declarations" and "net compatibility" sections. 3) There is no mention of how or where the Verilog-AMS data types can be used wrt. the 1364-2005 generate statements. Regards Graham -- ========================================================== Graham Helwig AMS Verification Australian Semiconductor Technology Company (ASTC) Pty Ltd Location: 76 Waymouth St, Adelaide, SA, 5000, Australia Phone +61-8-82312782 Moblie: +61-4-03395909 Email: graham.helwig@astc-design.com Web: www.astc-design.com ==========================================================Received on Tue May 23 17:23:33 2006
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