RE: minutes of Verilog-AMS call 23 May

Assuming that you are talking about regular string literals and regular
real or integer parameters, then SV is exactly like Verilog. It is an
integer to integer or real conversion. Integer to integer passes without
change unless the parameter is typed with a bit length shorter than the
string. Integer to real is obvious.

Shalom


> We talked a little about conversion of strings to real;
> this was previously an open issue as something that wasn't
> wanted.  The 2.2 LRM says it's an error to assign a string
> literal to a real or integer parameter, but this is
> somewhat "un-Verilog-like"
> 
> Action item: Geoffrey to check (with Shalom?) what SV
> does when converting to/from strings.