Re: minutes of Verilog-AMS call 23 May

Shalom -
I'm thinking about the case where I have a module with

    parameter real myparm = 1.0;

and then an instantiation that says
   .myparm("a string")


Is the parameter override legal?  What value do I get for myparm
when the module tries to use it?  If "a string" is treated as an
integer but the value is larger than MAXDOUBLE, what happens?

-Geoffrey


"Bresticker, Shalom" wrote:
> 
> Assuming that you are talking about regular string literals and regular
> real or integer parameters, then SV is exactly like Verilog. It is an
> integer to integer or real conversion. Integer to integer passes without
> change unless the parameter is typed with a bit length shorter than the
> string. Integer to real is obvious.
> 
> Shalom