Hello Arpad, This is not allowed in the LRM. However, if conditional event control statements were allowed in analog block then it would provide a common mechanism to enable/disable any event function (include digital event functions) within the analog block.Then the big question with conditional event control statements is what to do about the event function's internal state when it is enabled part way through a simulation? Here are my thoughts on the matter. Looking at constant event control statements, they are effectively enabled at time zero along with the rest of the simulation. As a result the first time point (time zero) behavior is different to subsequent time point's behavior because the event functions internal state information is being initialized. For conditional event control statements, the first time point after being disabled can be treated as a initialization time point (like at time zero), the event function are initialized using the current values of from the simulation. Regards Graham Muranyi, Arpad wrote: > Can events be disabled by putting them into > an IF statement? Or is that not allowed? > > Thanks, > > Arpad > ============================================ > > -----Original Message----- > From: owner-verilog-ams@server.eda-stds.org [mailto:owner-verilog-ams@server.eda-stds.org] On Behalf Of Sri Chandra > Sent: Friday, June 16, 2006 7:33 AM > To: Geoffrey.Coram > Cc: Ken Kundert; VerilogAMS Reflector > Subject: Re: Merged version of chapter 6 > > > Geoffrey, > > I dont think the few simulators that i have come across have implemented > what Ken was referring to - ie. disabling cross when direction is not > one of the three values. Hence i was bit concerned about interpreting > the syntax in this fashion now as it would not be compatible. V1.0 is > way too early for me to comment on the background of it. > > I also want to be careful to allow syntax for disabling syntax unless we > clearly identify/define the behavior when an active event is disabled > and also when an event is re-enabled. > > Finally, as i have mentioned earlier might be good to look at events in > general w.r.to disabling feature and how best to support it. > > cheers, > Sri > > > Geoffrey.Coram wrote: > >> I guess there are two possibilities that might have been implemented: >> 1) other values disable the cross >> 2) any positive value is interpreted as +1, any negative as -1 >> >> Ken says that Cadence uses (1). Are there any simulators that do (2)? >> >> The sentence I copied from the LRM seems to indicate that it would be >> an error to use a value other than 0,+1,-1 (though the LRM doesn't >> quite use IEEE-standard language (shall)). >> >> -Geoffrey >> >> >> >> Sri Chandra wrote: >> >>> event. I am not sure how many implementations interpret it in that >>> fashion ie. arguments not +1, 0, -1 disable the cross, and this is going >>> to lead to compatibility issues with existing implementations. >>> >>> > > > > > -- ========================================================== Graham Helwig AMS Verification Australian Semiconductor Technology Company (ASTC) Pty Ltd Location: 76 Waymouth St, Adelaide, SA, 5000, Australia Phone +61-8-82312782 Moblie: +61-4-03395909 Email: graham.helwig@astc-design.com Web: www.astc-design.com ==========================================================Received on Sun Jun 18 18:08:54 2006
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