Re: Regarding support of wreal

Bresticker, Shalom wrote:
> All that modeling in Verilog is using 64-bit real Verilog variables. The
> V and I were not attributes of 1-bit wires.
>   
For AMS V, I and logic are alternate views of a wire that are not 
mutually exclusive.
> I've just been explaining why wreal is so different from wire, and it
> does not make sense to look at wreal as just another type of the Verilog
> wire kind.
>   
Still disagreeing.
> It is an entity with analog attributes, whereas wire is an entity with
> digital attributes.
>   
As above, analog and digital properties are not mutually exclusive.
> Yes, you can add such entities to Verilog, as V-AMS has done, and map
> between the different types of entities, but from the point of view of a
> simulator, they are quite different types of constructs. 
>   
Not really, a discrete valued net will be handled much the same whether 
the type of it's drivers and receivers are real, integer or logic.
> It just does not make sense to say, if wires can be arrays or structs,
> why can't they be wreals? That is comparing apples and oranges, to be
> trite.
>   
What Verilog and VHDL both fail to do is give the user a way to indicate 
a type is an abstract type or a physical type, i.e. if you say a wire is 
of type 'real' it is not currently possible to indicate that you mean a 
64 bit bus or a single wire carrying a voltage - this is an extension 
that needs to be added. E.g. if you have a wire carrying an RF signal 
you might want to use a complex array to express it's value, but it is 
still only one physical wire, and it should be allowed to connect to 
other physical wires (maybe with different types of drivers) in the same 
domain as you can in the real world. Whether or not  "wires" carrying 
different abstract types can be joined is a separate debate.
> I'm not against wreals, just saying you have to understand that the
> difference between wreals and Verilog wires is fundamental to the
> language.
>
> Shalom
>   
They aren't that different, however I'd still like to dump wreal in 
favor of just being able to drive a discrete real value (voltage) onto a 
disciplined net - that way you can just read it back as a voltage or as 
a logic value (using automatic A2D) as needed in other modules.

Kev.
>   
>