RE: Regarding support of wreal

All that modeling in Verilog is using 64-bit real Verilog variables. The
V and I were not attributes of 1-bit wires.

I've just been explaining why wreal is so different from wire, and it
does not make sense to look at wreal as just another type of the Verilog
wire kind.

It is an entity with analog attributes, whereas wire is an entity with
digital attributes.

Yes, you can add such entities to Verilog, as V-AMS has done, and map
between the different types of entities, but from the point of view of a
simulator, they are quite different types of constructs. 

It just does not make sense to say, if wires can be arrays or structs,
why can't they be wreals? That is comparing apples and oranges, to be
trite.

I'm not against wreals, just saying you have to understand that the
difference between wreals and Verilog wires is fundamental to the
language.

Shalom

> -----Original Message-----
> From: Jonathan David [mailto:jb_david@yahoo.com]
> Sent: Tuesday, August 08, 2006 12:02 PM
> To: Bresticker, Shalom
> Cc: verilog-ams@eda.org
> Subject: Re: Regarding support of wreal
> 
> It modeled the control voltage on the control loop and the current
from
> the charge pump..
> But that method required that the ENTIRE pll be in one module..
> so that "REAL" variables could be used.. since they couldn't be
> connected from block to block..
> Bits2real would let you make the connection, but then the model has a
> different size port than the actual circuit.
> 
> With AMS you can use the normal logical models of the PFD, and the
input
> and reference dividers and Sigma Delta Modulator,
> feed the output of the CP as a current to the loop filter and the
output
> of the loopfilter as wreal to the VCO.. model, who's output is again
> digital..
> 
> If the VCO is feeding the input Mixer of an RF circuit.. its a little
> more interesting.. but you can keep the RF side out of the analog
solver
> until after the filter that follows the down converter..
> (I've done this once - I can do it again, for the right consulting
fee)
> this leaves much lower frequency signals in that Matrix  while you
> validate the transistor level circuit of the final ADC
> 
> The more you can do in the Event Driven solver, the less the Analog
> solver has to do..
> If I could ever get more than 50% of the CPU time to be taken by the
> Event solver, I'd feel I'd done a good job modelling.
> Jonathan
> 
> ----- Original Message ----
> From: "Bresticker, Shalom" <shalom.bresticker@intel.com>
> To: Jonathan David <jb_david@yahoo.com>; Kevin Cameron
> <kevin@sonicsinc.com>
> Cc: Sri Chandra <sri.chandra@freescale.com>; Verilog-A Reflector
> <verilog-ams@eda.org>; Martin O'Leary <oleary@cadence.com>
> Sent: Tuesday, August 8, 2006 1:35:17 AM
> Subject: RE: Regarding support of wreal
> 
> 
> Sure. I've done similar things. But did it assign the signals voltage
> and current levels?
> 
> > 5 years ago I ran across and (already old) paper on a model for a
PLL
> > circuit where all the integration for the "analog" nodes was written
> > behaviorally in Verilog..
> 
> Shalom