Geoffrey, First, I should say that I like the style: it is structured and readable. Still, I do think analysis() calls add to the comprehensability (?) of the code. Your examples below obviously give the wrong, i.e. bad use of analysis codes. However, wouldn't you agree that analysis("nodeset"), analysis("static") and analysis("ic") refer more to phases during the simulation, irrespective of the actual simulation type? So using f.ex. analysis("nodeset") to restrict execution of the geometry processing and f.ex. analysis("static") for the thermal processing would not have the problems you indicate below with explicit analysis types, but would have the advantages of making the limited execution of these initializing sequential blocks explicit. Marq Marq Kole Competence Leader Analog Simulation, Philips ED&T "Geoffrey.Coram" <Geoffrey.Coram@analog.com> Sent by: owner-verilog-ams@server.eda.org 28-08-2006 14:01 To verilog-ams <verilog-ams@server.verilog.org> cc Subject Re: initial_step and final_step in DC sweep Classification Marq - I am, indeed, relying on compiler optimizations. Borrowing again from my BMAS presentation, what if you did if (analysis("noise")) begin // Extended noise equations (6.103)..(6.113) end and then ran this in a PNoise analysis. Since "noise" matches only standard Spice small-signal noise, you would get no noise in a PNoise analysis. Neither the LRM nor the compact model author should have to worry about keeping track of all the different types of noise analyses and explicitly coding for them: if (analysis("noise","pnoise","hbnoise","qpnoise","xyznoise" ... //BAD! In another case, I saw a model that had the capacitance equations in analysis("tran") -- meaning that there would be no capacitance in an ac analysis, nor in PSS! I am content to have "wildly varying run times" and I will complain loudly to those vendors that have the longer run times. I am not content to have discrepancies between ac and tran, or tran and PSS, because model writers have tried to work around limitations of the compiler. -Geoffrey Marq Kole wrote: > > Geoffrey, > > I have taken a look at your MOS11 model: I see that you have totally abstained from using initial_step and final_step, but also from the analysis functions. I assume that you're relying on compiler optimizations that let the separate sequential blocks only be run when none of the module-scope variables they use changes value. Is that correct? Doesn't that introduce wildly varying run times in the various simulators? Wouldn't analog conditional statements be a more obvious guard against unnecessary execution of these blocks? > > MarqReceived on Mon Aug 28 05:36:14 2006
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